Dual damascene metal interconnects may enable reliable low cost production of integrated circuits using sub 0.25 micron process technology. Before such interconnects can realize their full potential, however, two problems related to the process for making them must be addressed. The first relates to the lithography for defining dual damascene vias and trenches. The second relates to the selectivity of certain materials, which are used to make dual damascene devices, to the etch chemistry used to etch the vias and trenches.
The lithographic process used to define dual damascene features can be relatively complex. Unlike conventional processes, which only require patterning of vias, processes for making dual damascene structures also require patterning of line/space combinations for trenches that will be etched into relatively thick transparent layers of dielectric. Those dielectric layers lie on top of various other layers, which may be made of metal or other materials. Those layers have different optical properties. As a result, when light strikes the surface of such a substrate, it may be reflected in a non-uniform and uncontrollable fashion. Such non-uniformity may cause the critical dimension ("CD") control across the wafer to be poor.
Dielectric and organic anti-reflective coatings ("ARCs") may be used to reduce substrate reflection. Using such materials, however, does not solve the lithography and etch problems of current processes for patterning integrated dual damascene structures. As to structures made using organic ARCs, such structures may include defects that result from the difference in etch rate between the dielectric layer and the ARC. As to dielectric ARC containing structures, such structures may not adequately absorb light, at the wavelength used during the exposure step of the lithographic process, to significantly reduce or eliminate the reflection problem.
In addition to the lithographic problem, the selectivity to certain etch chemistry of the dielectric layer to the underlying etch stop material must be reduced. Copper may be used to fill the trenches and vias, which were previously formed within a dielectric material, when forming a dual damascene structure. To make such a device, a thin layer of silicon nitride may be formed on top of an underlying copper layer to protect that layer from processes used to clean the previously etched via and trench. When the via and trench are formed within a silicon dioxide layer, an etch chemistry having a very high selectivity for silicon dioxide over silicon nitride must be used when forming the trench.
Trenches formed by such a process may be between about 3,000 and about 16,000 angstroms deep. When forming such trenches, a selectivity of silicon dioxide to silicon nitride of between about 17 and about 50 (or even greater) may be required to prevent the trench etch process from etching through the exposed portion of the silicon nitride layer, located at the bottom of the via.
Developing an etch chemistry that provides such high selectivity may be difficult. In addition, the degree of selectivity may be inversely proportional to the quality of the profiles and etch bias that result from the etch process. This effect may make it difficult to balance the need for high selectivity with the desirability of acceptable profile and etch bias performance to ensure correct patterning. If the selectivity is too high, the etch process may adversely impact via and trench profiles or increase the density of defects, e.g., from excessive polymer build-up. In addition, a relatively thick silicon nitride layer may be required to ensure that the trench etching step will not break through the silicon nitride to the underlying copper. Use of such a thick layer may not be practical if it negatively impacts the dielectric layer's overall dielectric constant.
One way to address this problem is to form an etch resistant plug within the via, prior to the trench etch step, to prevent the silicon nitride barrier layer from being exposed to chemistry used during the trench etching and cleaning process. An organic material, such as photoresist, or an organic ARC may be used to form such an etch resistant plug. However, because of the difference in etch rates between such an organic based plug and the dielectric layer, patterning defects known as "shells" or "fences" may form during the patterning of the dual damascene structures. Eliminating such defects without breaking through the silicon nitride layer may be a difficult process.
Accordingly, there is a need for a process that solves both the lithography and etch problems that may arise in current processes for forming dual damascene structures. There is a need for a process that transforms a typical reflective substrate into a non-reflective one that absorbs light during the lithographic process. There is also a need for a process for patterning a trench and via for making an integrated circuit having a copper containing dual damascene structure, which does not require use of a high selectivity etch to form the trench. There is a need for a method for forming such a structure that may provide superior via and trench profiles, which are substantially vertical, while generating fewer defects. In addition, there is a need for a process that permits the use of a thinner silicon nitride layer over an underlying copper layer. Using such a thin layer increases the ratio of silicon dioxide (or other material used to form the dielectric layer) to silicon nitride thickness, which should enhance the device's dielectric properties.